Akademik Sunum

Sıra	DOSYA ADI	Format	Bağlantı
01.	Rabbit Memory White Block	pptx	Sunumu İndir Sunuyu İndir Sunumu İndir

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, MadridWhite RabbitandKM3NeTPeter Jansweijer, on behalf of KM3NeT1&

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid1. Intro:◦ A multi-km3 neutrino telescope in the deep-sea2. KM3NeT daq from a technical perspective2Outline

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid3Potential neutrino sourcesSupernova RemnantsPulsar Wind NebulaGamma-Ray Burst ?Dark Matter ? ?? ??????Active Galactic NucleiCosmogenicneutrinosMicro Quasars

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid4Detection methodActive Galactic NucleineutrinomuonCherenkov lightNeutrino-induced muons in the deep seaStrings with optical sensor modules

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid5DeploymentActive Galactic Nuclei640 string with optical sensors in the deep sea at 3-5 km depth

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid6KM3NeT Artist Impression100m~ 860m640 strings20 DOM/string12800 DOMsVolume: ~5 km312,800 DOMs in the deep sea at 3-5 km depthwith point-to-point connection to shore

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid7Digital Optical Module (DOM)Upper Hemisphere12 PMTsLower Hemisphere19 PMTsCentral Logic Board(CLB)PMT Base:High Voltage SupplyAnalog Front-End

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, MadridReadout 31 TDC’s with 1 ns resolution“Knowledge” of absolute time (1 ns resolution)Data pushed from PMTs to Shore StationI2C: PMT-HV, Threshold, Compass, TiltOther IO: Temp, Nano beacon, AcousticsFirmware must be reconfigurableLow PowerLow CostPart of a scalable system (with respect to the complete detector)Highly reliable8Central Logic Board (CLB)

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid9White Rabbit is going deep-sea!

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid10Central Logic Board (CLB)Rx_mac2buf2nd CPULM32MEM I2CUARTFifo31 TDCsTDC0Management& ControlDataControlWishbone shared bus (32 bits)RxPacketBuffer64KBIP/UDP Packet BufferStream Selector (IPMUX)Rx_buf2dataRxPort 1RxPort 2RxPort_mManagement& Config.Tx_pkt2macTx_data2bufTxPort 1TxPort 2TxPort_mFlagsRx Stream SelectTxPacketBuffer32KBFlagsTx Stream Select31 PMTsUTC time & Clock (PPS, 125 MHz)Pause FrameADCManagement& ControlHydrophoneState MachineFifoTDC30FifoNanoBeaconGPIODebug LEDsI2CDebug RS232Temp CompassTiltPoint to Point interconnectionXilinxKintex-7

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, MadridShore Station11WR SwitchServer1192.16.x.1Time SliceIP192.16.x.11192.16.x.22::192.16.y.zn1. Each DOM synchronizes to the absolute time (using White Rabbit)2. Each DOM receives a look up table with IP addresses while configuring the detector.3. All DOMs start at an absolute point in time which was communicated via a command over the White Rabbit network.4. All DOMs start their first time-slice at exactly the same time.5. All data is IP/UDP formatted and passed to the IP number corresponding to the time slice6. After ‘n’ time slices, first PC is again selected to process the dataGPS PPS10MHzShoreSub SeaSwitchBuffersDOM1DOM2DOM16WR SwitchDOM12798DOM12799DOM12800Time SliceIPIP AddressServer2192.16.x.2Server n192.16.y.zServer Server Server ServerServers may beused for storage andPre-processing

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, MadridWork to be done(with respect to White Rabbit)There is no PCIe in the deep sea…◦Debug via UART◦Firmware reconfigurable; (new) software loaded together with (new) FPGA configuration (Block Memory Mapping file)Explore the Kintex-7 deterministic latency GTX◦Future Artix-7 may be even more cost effective in terms of money and powerImplement Oscillators, DACs (used by Soft-PLL) and SFP on FMC card which is to be plugged onto Xilinx KC705 Evaluation board (Mesfin Gebyehu)1st goal: Replace the (slave) SPEC in the SPEC<-> SPEC test setup with the KC705 implementation for validation.Study Shore Station (e.g. White Rabbit Switch v3) broadcast12

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, MadridTo be studied: Network BroadcastDOMDOMDOMDOMBufferBufferBufferBufferSFPSFPSFPSFPBroadcastOpticalNetworkStartTxt4 Stop1ReferenceClockPTPTime Stamp t1Time Stamp t4t4 Stop2Time Stamp t4t4 Stop3Time Stamp t4t4 Stop4Time Stamp t4Shore Station interface13Rxj: DDMTDRxj: DDMTDRxj: DDMTDRxj: DDMTDSFPMain Electrical Optical Cable(MEOC)May be 100 Km long…Can this be done with the WR Switch-V3?Need Firmware/Software change?

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid14Thank you!(White Rabbit community)

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid15Backup Slides

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid16LM32, three boot types1. Generate ROM image before synthesis (used for functional simulation debug)Describe a generic RAM using “init” fileUseful for functional simulationIncorporates “boot.elf” in the block-rams2. Download “elf” via an external interface in a running system (used for software debug)Useful for debugging purposes (the SPEC uses PCIe or JTAG)No BMM=Block Memory Mapping file needed3. After Place&Route (will be used in final CLB)Merge “FPGA.bit” file and “boot.elf” file (data2mem)This needs BMM=Block Memory Mapping fileThe “bit” file which is outputted by the merge can be used as updated configuration fileThis avoids synthesis each time software is updated

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, Madrid17BMM (Block Memory Mapping) FileFpga.bitROMRAMRAMB36RAMB360x000x00RAMB36RAMB360x000x00Fpga_elf.bitROMRAMRAMB36RAMB360x120x34RAMB36RAMB360x560x78hello.elfData2MemADDRESS_SPACE lm32_memory RAMB36 [0x00000000:0x00011FFF] BUS_BLOCK u1_u0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [31:30]; : END_BUS_BLOCK;END_ADDRESS_SPACE;ADDRESS_SPACE lm32_data_memory RAMB36 [0x00000000:0x00011FFF] BUS_BLOCKu6_u0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_init.ram/NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [31:30]; :END_BUS_BLOCK;END_ADDRESS_SPACE;fpga.bmm

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PeterJansweijerNikhefAmsterdamElectronics- TechnologyNovember 28, 2012 7th White Rabbit Workshop, MadridOptical Network (Simplified)18λ2λ2λ3λnA1REAM2xCu DOM1PINA2 DOM2DOMnREAM2xCuPIN2xCuPINJunction Boxλnλnλ2λ1DU-containerShore stationλ2- λnλ3Mod λ1λ2λ1λ2λ1λnλ3REAMλ1BroadcastMultiple lSlow Control l1Single lC2

Transkript

Rabbit Memory White Block

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